1. Field of the Invention
The present invention relates to a switching system, and more particularly, a duplexing processor in a switching system and method thereof.
2. Background of the Related Art
In general, a switching system includes a plurality of processors, which are required to process data on a real time basis, and are managed by a duplexing channel to prevent an interruption in processing of data even when a malfunction occurs. A duplexing channel is generally formed through a back plane between two processor boards having the same construction. While one processor is operating in an active mode, the other processor is operating in a standby mode. When a disturbance occurs at the active mode processor, the standby mode processor is switched to an active mode to successively perform the data processing.
As the processor is switched oil duplexing, the memories of the two processors should be identical to each other in order for the CPU of the standby processor to successively perform its normal operation. For this purpose, when the CPU of the active processor performs a data writing operation on its memory, it performs a concurrent writing operation when the data is one to be concurrently written into the memory of the standby processor. Accordingly, the same data is written into the same address of the memory of the active processor and into the memory of the standby processor. In order to identify whether the concurrent writing was successfully performed, the CPU of the active processor periodically compares the two memories of the two processor, thereby maintaining a coherency of the memories of the active processor and the standby processor.
The operation of the background art duplexing processor will now be described with reference to FIG. 1. The duplexing processor of the switching system consists of an active processor 10 and a standby processor 20 that are connected to each other through a duplexing bus. The active processor 10 and the standby processor 20 respectively include a CPU 11 and 21, a memory 12 and 22, a concurrent write logic unit 13 and 23, and a standby read logic unit 14 and 24.
The CPU 11 of the active processor 10 performs three kinds of operations: (1) a self-reading and writing operation for reading or writing only its own memory (active memory 12); (2) a concurrent writing operation for concurrently writing the same data also on the memory (standby memory 22) of the standby processor when writing the data on the active memory 12; and (3) a standby reading operation for reading a data of a corresponding arbitrary address of the standby memory 22 to compare it with the data written in the arbitrary address of the active memory 12 to check whether the concurrent writing operation was correctly performed.
The three operations are divided by an agreement between a software and a hardware. For example, regarding xe2x80x9868000/68020/68030xe2x80x99 type CPUs in the line of 68XXX processors, the three operations are performed according to classification of an address field value, and a logic of the hardware is driven according to the address field value. While the three operations are performed by a UPA0/UPA1 (UPA: User Page Attributes) of the CPU with respect to xe2x80x9868040/68060xe2x80x99.
For example, on the assumption of 128 Mbyte memory, the operation of the CPU are as shown Table 1 as follows:
In this manner, when the operation state of the CPU 11 is represented according to the setting of the address field value or the UPA bit value previously determined on the basis of software, the hardware drives logic that is suitable for the operation.
When an address field value or a UPA bit value corresponding to the xe2x80x98(2) concurrent writingxe2x80x99 operation of Table 1 is applied from the CPU 11, the concurrent write logic unit 13 accesses the memory 22 of the standby processor through the duplexing bus and writes the same data into the two memories 12 and 22. When an address field value or a UPA bit value corresponding to the xe2x80x98(3) standby readingxe2x80x99 operation of Table 1 is applied from the CPU 11, the standby read logic unit 14 accesses the memory 22 of the standby processor through the duplexing bus and reads the data of the memory 22 to transfer it to the CPU 11. The three operations of the background art duplexing processor will now be described.
1. Self Reading and Writing Operation
This operation is performed when the data written in the active memory 12 is desired to be read by the CPU 11, and when the data is desired to be written only in the active memory 12. That is, the data written into the memory 12 is not written into the standby memory 22 because the data wouldn""t affect the operation of the CPU 22.
First, the CPU 11 sets an address field value or a UPA bit value corresponding to the xe2x80x98(1) Self reading and writingxe2x80x99 operation of Table 1 and selects an address desired to be read or written. The units 13 and 14 corresponding to the duplexing logic are not driven, and only the corresponding active memory 12 is accessed. Thus, the data of the corresponding address is read or written.
2. Concurrent Writing Operation
This operation is performed when the data is desired to be concurrently written into the active memory 12 and the standby memory 22 by the CPU 11. First, the CPU 11 sets an address field value or a UPA bit value corresponding to the xe2x80x98(2) concurrent writingxe2x80x99 operation of Table 1 and outputs a data to be written and its address. Thereafter, the data is written into the corresponding address of the active memory 12, and simultaneously, the concurrent write logic unit 13 is driven.
The concurrent write drive unit 13 accesses the memory 22 of the standby processor and transfers the same data as the data transferred to the active memory 12 through the duplexing bus. Accordingly, the same data as that written in the active memory 12 is written into the corresponding address of the standby memory 22.
3. Memory Coherency Maintaining Operation
This operation is performed to periodically identify whether the same data was written in the active memory 12 and in the standby memory 22 by means of the CPU 11 of the active processor 10. Memory coherency enables the CPU 21 of the standby processor 20 to be able to continuously perform the operation of the previous active processor in case of the duplexing switch.
First, the active memory 12 is accessed and a data written in the corresponding address of the memory 12 is applied to the CPU 11. Thereafter, when the CPU 11 selects the address field value or the UPA bit value corresponding to the xe2x80x98(3) standby readxe2x80x99 operation of Table 1 and the same address as above, the standby read logic unit 14 is driven.
The standby read logic unit 14 accesses the memory 22 of the standby processor, reads a data of a corresponding address of the memory 22 and transfers it to the CPU 11 through the duplexing bus. Thereafter, the CPU 11 compares the data as read from the active memory 12 and the data as read from the standby memory 22. If the two data are identical, the CPU 11 repeatedly performs the above process to thereby compare the data of the next address.
Meanwhile, upon such comparison, if the two data of the memories 12 and 22 are not identical, the CPU 11 sets a field value of the discordant address or a UPA bit value corresponding to the xe2x80x98(2) concurrent writtingxe2x80x99 operation of Table 1. Accordingly, the concurrent write logic unit 13 is driven so as to transfer a data of a predetermined address of the active memory 12 to the standby memory 22 through the duplexing bus. In this manner, the same data as the data written in the active memory 12 is written into the corresponding address where the discordance occurred of the standby memory 22.
FIGS. 2A and 2B show views of timing of an example of the memory coherency maintaining operation of the duplexing processor. FIG. 2A shows the case where the two memories are identical, and FIG. 2B shows the case where the two memories are not identical.
Referring to FIGS. 2A and 2B, in the case where the CPU 11 compares the data of a specific address, i.e., xe2x80x980x1000xe2x80x99, it sets the address as xe2x80x980x1000xe2x80x99 to represent a self-reading operation and accesses the active memory 12 to read a corresponding address value. Thereafter, the CPU 11 sets the address as xe2x80x980x40001000xe2x80x99 so as to represent a standby reading operation, and drives the standby read logic unit 14 to receive the corresponding address value of the standby memory 22.
The CPU 11 compares the data read from the two memory 12 and 22. As shown in FIG. 2A, if the two data as read are equal(i.e., xe2x80x980x0123xe2x80x99), it sets the next address to be compared (i.e., xe2x80x980x1004xe2x80x99). The CPU 11 then repeatedly performs the same process described above.
Meanwhile, as shown in FIG. 2B, if the two data as read are not equal (i.e., xe2x80x980x0123xe2x80x99 and xe2x80x980x012Fxe2x80x99), the CPU 11 again reads the data xe2x80x980x0123xe2x80x99 of the corresponding address xe2x80x980x1000xe2x80x99 of the active memory 12 and then drives the concurrent write logic unit 13 to concurrently writes the data xe2x80x980x0123xe2x80x99 into the active memory 12 and the standby memory 22.
Thereafter, the CPU 11 performs comparing operation for the next address (i.e., xe2x80x980x1004xe2x80x99) using the same process as described above. Thus, the process for maintaining the memory coherency in the background art duplexing processor is performed by reading the data of the active memory, reading the data of the standby memory, comparing the two data, and performing the concurrently writing operation according to the comparison result.
As described above, the background art duplexing processor has various disadvantages. The CPU of the active processor performs each step by contiguously changing the address values needed to perform each operation and compares the data on the basis of software, which results in a lengthy time for the operation and a load of the CPU is increased. Thus, because of the verification time limit and the restraint of the load of the CPU, it is hard to perform such a verification function while the processor is actually in service (i.e., processing of a call of actual subscribers, or billing). Accordingly, the reliability of the processor is reduced.
The above references are incorporated by reference herein where appropriate for appropriate teachings of additional or alternative details, features and/or technical background.
An object of the invention is to solve at least the above problems and/or disadvantages and to provide at least the advantages described hereinafter.
Another object of the present invention is to provide a switching system processor and method that substantially obviates one or more of the problems caused by disadvantages in the background art.
Another object of the present invention is to provide a duplexing processor operated in a standby and active mode that maintains coherent memory and method thereof.
Another object of the present invention is to provide a duplexing structure of a switching system processor and method in which both data of an active memory and of a standby memory are concurrently read and the data as read are compared on the basis of hardware for maintaining a memory coherency.
To achieve these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a switching system having a duplexing channel between two processors each adapted to operate in an active mode and a standby mode, each processor that includes a memory, a CPU that generates a control signal for concurrently reading a selected memory address to be compared, a concurrent read logic unit that concurrently accesses memories of an active processor and a standby processor responsive to the control signal of the CPU and reads data from the selected addresses in the memories, a comparator that compares the two data from the selected address of the memories of the two processors, and a concurrent read termination generator that generates a prescribed termination signal according to a comparison result by the comparator.
To further achieve these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a method for maintaining a memory coherency of a switching system processor having a duplexing channel between two processors that each mutually operate in an active mode and a standby mode, respectively, that includes generating a prescribed control signal to perform a concurrent reading operation for an arbitrary memory address, concurrently accessing memories of the active and standby processors, respectively, to read data from the arbitrary address of both memories responsive to the control signal, comparing the data read from the two processor memories, and generating a termination signal according to a comparison result.
To further achieve these objects and other advantages in a whole or in part and in accordance with the purpose of the present invention, as embodied and broadly described herein, there is provided a switching system having a data bus between a plurality of processors each adapted to operate in an active mode and a standby mode, wherein at least one processor is in the active mode mid remaining processors are in the standby mode, each processor that includes a memory, a CPU that generates a control signal for concurrently reading a selected memory address to be compared, a concurrent read logic unit that concurrently accesses memories of the at least one active processor and the standby processors responsive to the control signal of the CPU and reads data from the selected addresses in the memories, a comparator that compares the data from the selected address of the memories of the processors, and a concurrent read termination generator that generates a prescribed termination signal according to a comparison result by the comparator.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.